1) Field of the Invention
The present invention relates to, for example, in an information processing system comprising a plurality of components between which interchange of data takes placer an automatic clock tuning method, an automatic clock tuning control system and an apparatus having an automatic clock tuning function, each of which accomplishes automatic tuning of a phase of a clock to transmission latch or receive latch in each of the components so that the transfer of data between these components is achievable within a predetermined number of clock cycles.
2) Description of the Related Art
In general, an information processing system is constructed as a cluster in which, for example, a plurality of components (CPU, and others) are connected to a single control unit.
In addition, in such an information processing system, the transfer of data among components is performed surely within a predetermined number of clock cycles (for example, one clock cycle) through the use of a plurality of types of system clocks different in phase from each other, thereby enhancing the efficiency of the data transfer.
Concretely, allowing for a data transfer delay corresponding to a length of a data bus between the components, a system clock [E (Early) clock] advancing somewhat in phase with respect to a normal system clock [N (Normal) clock] is supplied to a transmission latch for sending data to a data bus in a component on the transmission side, while a system clock [L (late) clock] retarding somewhat in phase relative to the normal system clock is given to a receive latch for receiving data from a data bus in a component on the receive side.
Therefore, data from the transmission side to the receive side is forwarded through a transmission latch to a data bus on the somewhat early side (somewhat early), while the receive latch latches data from a data bus on the somewhat late side (somewhat latish).
Such adjustment of the phase of the system clock to the transmission buffer or the receive buffer enables reliable data transfer among the components within a predetermined number of clock cycles without suffering the effects of a data transfer delay stemming from the length of the data bus. Incidentally, needless to say, such system clock phase adjustment will be made in a manner of avoiding reflecting on the data transfer in each of the components.
Furthermore, in general, prior to the information processing system being put on the market, such system clock relative phase adjustment or absolute phase adjustment is made manually through the use of a tester dedicated to clock tuning to optimize (accomplish the clock tuning) the relationship in phase among the aforesaid plurality of types of system clocks.
Meanwhile, with the enlargement in information processing system scale, extension (additional installation) or replacement in units of components in the information processing system constitutes an effective and important means for improvement of performance or maintenance of the information processing system. If a portion undergoing such extension or replacement forms a portion of a central processing unit (CPU), that extension/replacement requires quick work and, particularly, high reliability. Therefore, there is a need to facilitate the extension/replacement on the user side of the information processing system.
For realizing the facilitation of the extension/replacement, regardless of the function of a device to be additionally installed or replaced (particularly, even if a device to be replaced has the same function as that of the device before the replacement or has a newly added function), there is a need to optimize the relationship in phase among a plurality of system clocks so that the data transfer between the components is surely achievable within a predetermined number of clock cycles and a trouble to the data transfer in each of the components is a voidable.
For this reason, a method called xe2x80x9coperating margin guaranteexe2x80x9d has been put to use. That is, in performing the manual clock tuning through the use of the clock tuning dedicated tester as mentioned above, this is for securing a larger range in which the relationship in phase among the aforesaid plurality of system clocks is optimal, thereby absorbing the physical differences between the devices to be additionally installed or replaced or the differences resulting from the functions thereof. Thus, in addition to the operational margin needed for the real operation, the foregoing operating margin includes an operating margin which can accept the aforesaid extension/replacement work.
However, as stated above, the current clock tuning has been conducted manually through the use of the clock tuning dedicated tester prior to the information processing system being put on the market, which has required a great labor penalty.
In addition, as stated above, since, in addition to the guarantee on the operating margin needed for the real operation, the clock tuning has been conducted while providing guarantee of an operating margin taking into consideration devices to be additionally installed or replaced after the installation of the information processing system, a considerably larger operating margin than needed actually becomes necessary. For this reason, an increase in system scale or an enlargement in system operating frequency, the ratio of the operating margin to the operating frequency increases, which makes it difficult to secure the operating margin. Contrary to this, the enlargement of such an operating margin securing range sometimes imposes the limitation on the system performance, such as reducing operating frequency.
Meanwhile, if, whenever an alteration or change of system configuration takes place, the relationship in phase among a plurality of system clocks can be optimized according to the device alteration, then it is possible to eliminate the need for wasteful guarantee of an operating margin for the device to be additionally installed or replaced, which allows an operating frequency corresponding to a system performance to be set, thus eliminating the limitation on the system performance.
Accordingly, the present invention has been developed with a view to solving the above-mentioned problems, and it is therefore an object of the invention to provide an automatic clock tuning method, an automatic clock tuning control system and an apparatus having an automatic clock tuning function, which are capable of automatically and quickly optimizing the relationship in phase among clocks at installation of a system or at extension thereof for cutting the labor needed for the clock tuning, and further of securing only an operating margin needed for the real operation without providing guarantee on a useless operating margin, thus exhibiting the maximum of system performance.
For this purpose, in accordance with the present invention, there is provided an automatic clock tuning method of automatically tuning a phase of a clock to a transmission latch for sending data to a data bus in a transmission side component and a phase of a clock to a receive latch for receiving data from a data bus in a receive side component, comprising an operation of adjusting the phase of the clock to the transmission latch in the transmission side component, an operation of generating a data pattern for a clock phase check in the transmission side component, an operation of switching a circuit in the transmission side component to send the data pattern through the transmission latch to the data bus, an operation of adjusting the phase of the clock to the receive latch in the receive side component, an operation of verifying, on the basis of the data pattern received by the receive latch from the transmission side component, as to whether or not the data transfer from the transmission side component to the receive side component is accomplished within a predetermined number of clock cycles, and an operation of adjusting the phase of the clock to the transmission latch and the phase of the clock to the receive latch according to a verification result of the verifying operation so that the data transfer from the transmission side component to the receive side component is accomplished within the predetermined number of clock cycles.
At this time, in a case in which a phase range of the clock to the transmission latch and a phase range of the clock to the receive latch which allow the data transfer from the transmission side component to the receive side component to be accomplished within the predetermined number of clock cycles are obtained on the basis of the verification result of the data pattern verifying operation, the phase of the clock to the transmission latch and the phase of the clock to the receive latch are adjusted to the medians of the obtained phase ranges, respectively.
Furthermore, in accordance with the invention, there is provided an automatic clock tuning control system for automatically tuning a phase of a clock to a first transmission latch for sending data to a data bus in a first component, a phase of a clock to a first receive latch for receiving data from a data bus in the first component, a phase of a clock to a second transmission latch for sending data to a data bus in a second component and a phase of a clock to a second receive latch for receiving data from a data bus in the second component, the control system comprising a first clock phase adjusting circuit for adjusting the phase of the clock to each of the first transmission latch and the first receive latch in the first component, a second clock phase adjusting circuit for adjusting the phase of the clock to each of the second transmission latch and the second receive latch in the second component, a first data pattern generating circuit for generating a first data pattern for a clock phase check in the first component, a second data pattern generating circuit for generating a second data pattern for a clock phase check in the second component, a first switching circuit for switching a circuit in the first component to send the first data pattern, generated in the first data pattern generating circuit, through the first transmission latch to the data bus, a second switching circuit for switching a circuit in the second component to send the second data pattern, generated in the second data pattern generating circuit, through the second transmission latch to the data bus, a first data pattern verifying circuit for verifying whether or not the data transfer from the second component to the first component is accomplished within a predetermined number of clock cycles, on the basis of the second data pattern received by the first receive latch from the second component, a second data pattern verifying circuit for verifying whether or not the data transfer from the first component to the second component is accomplished within the predetermined number of clock cycles, on the basis of the first data pattern received by the second receive latch from the first component, and an automatic clock tuning control circuit for controlling the first clock phase adjusting circuit and the second clock phase adjusting circuit according to verification results of the first data pattern verifying circuit and the second data pattern verifying circuit, respectively, to adjust the phase of the clock to the first transmission latch, the phase of the clock to the first receive latch, the phase of the clock to the second transmission latch and the phase of the clock to the second receive latch so that the data transfer between the first component and the second component is accomplished within the predetermined number of clock cycles.
At this time, in a case in which a phase range of the clock to the first transmission latch, a phase range of the clock to the first receive latch, a phase range of the clock to the second transmission latch and a phase range of the clock to the second receive latch which allow the data transfer between the first component and the second component to be accomplished within the predetermined number of clock cycles are obtained on the basis of the verification results of the first data pattern verifying circuit and the second data pattern verifying circuit, the automatic clock tuning control circuit sets the phase of the clock to the first transmission latch, the phase of the clock to the first receive latch, the phase of the clock to the second transmission latch and the phase of the clock to the second receive latch at the medians of the obtained phase ranges, respectively.
In addition, it is also appropriate that, in the first component, the first data pattern verifying circuit verifies whether or not intra-component data transfer from a latch immediately before the first transmission latch to the first transmission latch and intra-component data transfer from the first receive latch to a latch immediately after the first receive latch are made within the predetermined number clock cycles, while in the second component the second data pattern verifying circuit verifies whether or not intra-component data transfer from a latch immediately before the second transmission latch to the second transmission latch and intra-component data transfer from the second receive latch to a latch immediately after the second receive latch are made within the predetermined number of clock cycles, and the automatic clock tuning control circuit controls the first clock phase adjusting circuit and the second clock phase adjusting circuit in view of the verification results of the first data pattern verifying circuit and the second data pattern verifying circuit to adjust the phase of the clock to the first transmission latch, the phase of the clock to the first receive latch, the phase of the clock to the second transmission latch and the phase of the clock to the second receive latch so that the intra-component data transfer in each of the first component and the second component is accomplished within the predetermined number of clock cycles.
In this case, it is also preferred that the first component includes an inverter for inverting an output of the latch immediately before the first transmission latch to re-input the inverted output as a data pattern for an intra-component clock phase check to the latch immediately before the first transmission latch and an inverter for inverting an output of the first receive latch to re-input the inverted output as a data pattern for an intra-component clock phase check to the first receive latch while the second component includes an inverter for inverting an output of a latch immediately before the second transmission latch to re-input the inverted output as a data pattern for an intra-component clock phase check to the latch immediately before the second transmission latch and an inverter for inverting an output of the second receive latch to re-input the inverted output as a data pattern for an intra-component clock phase check to the second receive latch.
Still additionally, it is also appropriate that, in the first component, a latch for holding a data pattern to be generated by the first data pattern generating circuit and a latch for holding a data pattern, received from the second component, in the first data pattern verifying circuit are combined into one latch, and in the second component, a latch for holding a data pattern to be generated by the second data pattern generating circuit and a latch for holding a data pattern, received from the first component, in the second data pattern verifying circuit are combined into one latch.
Still furthermore, an apparatus according to the invention comprises a transmission latch for sending data to a data bus, a receive latch for receiving data from a data bus, a clock phase adjusting circuit for adjusting the phases of the clocks to the transmission latch and the receive latch, a data pattern generating circuit for generating a data pattern for a clock phase check, a switching circuit for switching a circuit to send the data pattern, generated by the data pattern generating circuit, through the transmission latch to a data bus, a data pattern verifying circuit for verifying, on the basis of a data pattern received by the receive latch, whether or not the data transfer from the transmission latch to the receive latch is accomplished within a predetermined number of clock cycles, and an automatic clock tuning control circuit for controlling the clock phase adjusting circuit according to a verification result of the data pattern verifying circuit to adjust the phase of the clock to the transmission latch and the phase of the clock to the receive latch so that the data transfer among the latches is accomplished within the predetermined number of clock cycles.
At this time, in a case in which a phase range of the clock to the transmission latch and a phase range of the clock to the receive latch which allow the data transfer among the latches to be accomplished within the predetermined number of clock cycles are obtained on the basis of the verification result of the data pattern verifying circuit, the automatic clock tuning control circuit adjusts the phase of the clock to the transmission latch and the phase of the clock to the receive latch to the medians of the obtained phase ranges, respectively.
Moreover, it is also appropriate that the apparatus includes a plurality of components and the automatic clock tuning control circuit includes a configuration information comparing function to compare the present configuration of the components with the previous configuration thereof to recognize an alteration in configuration at the start-up of the apparatus, and when the configuration information comparing function recognizes the alteration in configuration, implements an automatic clock tuning operation.
In this case, it is also preferred that the automatic clock tuning control circuit specifies a place of the configurational alteration through the use of the configuration information comparing function, and operates the clock phase adjusting circuit, the data pattern generating circuit, the switching circuit and the data pattern verifying circuit to implement the automatic clock tuning operation for only the specified configuration altered place.
In addition, it is also preferred that the automatic clock tuning control circuit holds automatic tuning implementation information representative of whether or not an automatic clock tuning operation has already been implemented in the apparatus, and sees the automatic tuning implementation information to, when recognizing the fact that the automatic clock tuning operation has not been implemented yet, implement the automatic clock tuning operation for the entire apparatus.
Still additionally, it is also appropriate to include a plurality of components, a reserve data bus to be connected to a new component at a functional extension and a logic circuit for validating a verification result of a data pattern verifying circuit of the new component to be connected to the reserve data bus.
Thus, the automatic clock tuning method, automatic clock tuning control system and apparatus according to the present invention can offer the following effects and advantages.
(1) At installation or extension/replacement of an information processing system or the like, the relationship in phase between clocks can be optimized automatically and quickly without requiring a new inter-component signal or intra-component signal, which can reduce considerably the labor needed for clock tuning.
(2) No need for a new inter-component signal or intra-component signal for data transfer verification exists, which enables easy optimization of the relationship in phase among a plurality of system clocks even if the system configuration scale increases considerably with new system development or formation into microprocessor.
(3) Because of eliminating a guarantee of a useless operating margin and of allowing a guarantee of only the operating margin needed for real operation, which eliminates the limitation on the performance of the information processing system or the like to enable the exhibition of the maximum of performance thereof, thus providing a system with a high processing ability and a high reliability.
(4) Automatic clock tuning becomes possible on the user side (at the location of the information processing system or the like) so that the clock tuning becomes feasible under an actual operating environment, thus offering a higher-reliability system.
(5) The use of the configuration information comparing function permits the verification of only the relationship in phase among system clocks related to a place in which configurational alteration takes place, so that a verifying operation still needed by sufficient can be conducted at replacement of components or at alteration in configuration, thus offering a high-reliability system promptly.
(6) The installation of a control system (logic circuit) which can incorporate a reserve data bus into an object to be verified allows the verification of data transfer while coping flexibly with functional extension of the information processing system or the like.
(7) The unification of a latch for data pattern generation and a latch for data pattern verification cuts the number of shift registers, thus leading to the simplification of the system configuration.